Many PLL IC's with integrated LC voltage controlled oscillator (VCO) utilize a digitally programmable coarse tuning word in parallel with the fine tuning varactor. These PLL's require a digital coarse tuning system to select the appropriate digital coarse tuning word for the VCO. Furthermore, in order to reduce PLL bandwidth variation due to VCO tuning gain (Kv) variation, the VCO tuning gain Kv can be measured and compensated by adjusting charge pump current. As shown in FIG. 9, a frequency locked loop (FLL) system is employed to both select the appropriate coarse tuning digital word ct_val and to measure and compensate the VCO (106) tuning gain by modifying the charge pump 706 output current. An FLL differs from a PLL in that it detects frequency error rather than phase error and drives frequency error rather than phase error (as in a PLL) to zero. Since the VCO in an FLL does not act as an integrator converting voltage into phase, an FLL is a Type I (single integrator) control loop. Type I loops can be designed for very fast transient response. The FLL is used to perform coarse tuning (CT) and Kv calibration because of its inherent simplicity and its relatively fast transient response.
In the coarse tuning calibration sequence, the FLL controls the VCO coarse tuning (ct_val) directly. The coarse tuning FLL comprises the digital frequency detector 1006, the coarse tune digital loop filter 1206, and the VCO 106. The Kv calibration FLL comprises the digital frequency detector 1006, the Kv compensation digital loop filter 1106, the DAC 506, and the VCO 106. In the coarse tuning sequence, the coarse tune digital loop filter 1206 provides a coarse tuning digital word ct_val to the coarse tuning input port of the VCO 106. In the Kv calibration sequence, the Kv compensation digital loop filter 1106 drives the digital-to-analog converter (DAC) 506 to provide the VCO fine tuning voltage through the Vtune analog input port of the VCO 106. After the coarse tuning and Kv calibration sequences are completed the system exits FLL mode and enters PLL mode. Although, the FLL converges to zero frequency error very quickly and PLL mode is engaged with zero frequency error, it may still require a long acquisition time to phase lock using the circuit of FIG. 9. The phase lock time of a PLL has a strong dependency on the initial phase error at the input end of the phase frequency detector (PFD) 606. Since the FLL tracks frequency rather than phase, any signal traveling on the route of frequency divider 906, phase frequency detector 606, charge pump (CP) 706, and the loop filter (LPF) 806 is ignored during the FLL mode; and this initial phase error is random; therefore, the phase at the inputs to the PFD 606 remains arbitrary and random. Because the phase error can be any value after calibration it can take a relatively long time to lock the PLL even though the initial frequency error of the VCO is near zero.
FIG. 1 and FIG. 2 show the schematic of a 3-state phase detector common in the industry and its associated state diagram. FIG. 3-6 illustrate four different scenarios of the phase error value when the phase detector is first initialized assuming the UP=0, DN=0 is the reset state. These figures show cases were the frequency error is zero, (i.e. period of Fv is the same as Fr) as would be the case at the switchover from FLL to PLL mode in the system of FIG. 9.
FIG. 3-6 illustrate the relationship among the reference frequency (Fr), the divided frequency (Fv) generated by the frequency divider 906, the pump-up (PU) signal, and the pump-down (PD) signal. The PFD 606 receives both Fr and Fv, then provides the PU signal and PD signal to the charge pump 706 based on the phase difference between the Fr and Fv. These figures assume a system with both a positive Kv and a non-inverting loop filter (i.e. PU causes VCO to be pushed to higher frequency and PD pushes to lower frequency). In systems with negative Kv or an inverting loop filter the polarities shown in the figures can be adjusted accordingly.
FIG. 3 shows that the edge of the Fv is slightly beyond the edge of the Fr; therefore, the PU signal is provided to speed up the VCO and to push Fv to catch up with the Fr. FIG. 4 shows that the edge of the Fr is slightly beyond the edge of the Fv; therefore, the PD signal is provided to slow down the VCO and to cause the Fr to catch up with Fv. In both cases illustrated in FIG. 3 and FIG. 4, the PLL will force the VCO away from zero frequency error in order to accelerate or decelerate the phase so that the edges of Fv will catch up by occurring earlier or slow down by occurring later. Since the phase errors in FIG. 3 and FIG. 4 are relatively small, they do not require significant lock time, since the loop responds by pushing the VCO in the correct direction.
FIG. 5 and FIG. 6 illustrate the scenarios which do require significant lock time. FIG. 5 shows that the first rising edge of the Fv is slightly before the second rising edge of the Fr. Both Fv and Fr have the same period (frequency); however, since the first rising edge of Fr is essentially skipped, the PU signal is provided to speed up the VCO and to push Fv to catch up with the Fr. FIG. 6 shows that the first rising edge of the Fr is slightly before the second rising edge of the Fv; therefore, the PD signal is provided to slow down the VCO and to cause the Fv to slow down and sync with the Fr. In both cases illustrated in FIG. 5 and FIG. 6, the PLL will push the VCO away from zero frequency error in order to add or remove an entire clock cycle. This will cause the PLL to exhibit a significant lock time even though the initial frequency errors in FIG. 5 and FIG. 6 are zero.
FIG. 7 depicts a relationship diagram of a tuning voltage Vtune and a VCO frequency of a conventional VCO. If the system attempts to lock the PLL at the frequency Fi, and it encounters the phase error as illustrated in the FIG. 6, then the PLL will react as if the VCO is too fast and it will slow the VCO down. Because the VCO must slow down until an entire cycle is slipped, the tuning voltage will be pushed towards left and it will quickly hit the low supply rail because the VCO/LPF can't go lower than Vtune Minimum. FIG. 8 shows a plot of tuning voltage versus time in this scenario. If the VCO had a wider frequency tuning range, which permits the PFD to push the VCO and Fv as far in frequency as needed to skip/add a cycle as shown in the FIG. 5 and FIG. 6, then the lock time can be shortened because the nonlinearity at the supply rail would not be encounter. However, since a low Kv is desirable for minimizing phase noise, a wide tuning range for a VCO is not ideal in many applications.
There are few U.S. patents which use the analog “gear shifting” approach in enhancing the phase locking time. The U.S. Pat. No. 6,906,565 issued to Keaveney entitled “fast lock phase lock loop and method thereof”. The U.S. Pat. No. 6,504,437 issued to Nelson entitled “low-noise, fast-lock phase lock loop with gear shifting control”. The U.S. Pat. No. 6,940,356 issued to McDonald entitled “circuitry to reduce PLL lock acquisition time”. Each of these patents discloses increasing the PLL bandwidth during acquisition, and subsequently decreasing for low noise after lock is achieved. Bandwidth is changed by altering charge pump currents and/or loop filter resistor values. The analog method of the patent presents a challenge task in term of implementation; a glitch-free bandwidth switchover might be difficult to implement. In addition, these patents do not address PLL auto-calibration, which would cause additional lock time in all of these patents.
The U.S. Pat. No. 7,327,196 issued to Goldberg entitled “fast switching phase lock loop device and method”, which discloses a PLL having a voltage controlled oscillator that generates a signal at a frequency according to a received voltage. Goldberg discloses a memory holding a set of adjustment values. With each adjustment value set, the VCO can be tuned to a desired frequency. Goldberg requires a very accurate DAC and ADC, and Goldberg does not address the phase alignment issue, which can cause the long initial phase lock time even if initial frequency error is zero.
The U.S. Pat. No. 4,560,950 issued to Cabot entitled “method and circuit for phase lock loop initialization”. The U.S. Pat. No. 5,304,951 issued to Cosand entitled “divider synchronization circuit for phase-locked loop fast phase locking system”. These patents disclose that the PFD and N-divider are held in reset and initialized by a control signal until the next rising edge of the VCO. This helps the PLL to initialize with the PFD inputs near zero phase difference. However, these patents provide no measure to ensure that the VCO is at the correct initial frequency. These patents also do not pre-charge the loop filter. In addition, if there is pump up/down mismatch or leakage in the charge pump, the desired initial phase is not zero. Furthermore, these patents provide an alignment which only gets the PFD inputs close to the desired operation point.
In view of these current practices, there is a need to enhance the initial phase lock time before entering the PLL mode and yet ensure the VCO is operating at a desired frequency.